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CMOS IC
8-Bit Single Chip Microcontroller LC876764A/48A
Under Development
LC876764A
8 bit Single Chip Microcontroller incorporating 64KB ROM and 1536 byte RAM on chip
LC876748A
8 bit Single Chip Microcontroller incorporating 48KB ROM and 1536 byte RAM on chip
Overview
The LC876764A/LC876748A are 8 bit single chip microcomputers with the following on-chip functional blocks: - CPU: operable at a minimum bus cycle time of 100ns - On-chip ROM Maximum Capacity : LC876764A 64K bytes LC876748A 48K bytes - On-chip RAM: 1536 bytes - VFD automatic display controller / driver - 16 bit timer / counter (can be divided into two 8 bit timers) - 16 bit timer / PWM (can be divided into two 8 bit timers) - four 8 bit timer with prescaler - timer for use as date / time clock - High speed clock counter - System clock divider function - synchronous serial I/O port (with automatic block transmit / receive function) - asynchronous / synchronous serial I/O port - 14-channel x 8-bit AD converter - Weak signal detector - 21-source 10-vectored interrupt system All of the above functions are fabricated on a single chip.
Ver:1.01 80901
SYSTEM-BIZ Div. S. Kubota
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LC876764A/48A
Features
(1) Read-Only Memory (ROM): LC876764A 65536 x 8 bits LC876748A 49152 x 8 bits (2) Random Access Memory (RAM): LC876764A/48A (3) Minimum Bus Cycle Time: 100ns (10MHz) Note: The bus cycle time indicates ROM read time. (4) Minimum Instruction Cycle Time: 300ns (10MHz) (5) Ports - Input/output ports Data direction programmable for each bit individually : - 15V withstand input/output ports Data direction programmable in nibble units : (When N-channel open drain output is selected, data can Data direction programmable for each bit individually : - Input ports : - VFD output ports Large current outputs for digits : Large current outputs for digits / segments : digit / segment outputs : segment outputs : Other functions Input/output ports : Input ports : - Oscillator pins : - Reset pin : - Power supply : 1536 x 9 bits
20 (P1n, P70 to P73, P8n) 8 be 8 2 (P0n) input in bit units.) (P3n) (XT1,XT2)
9 (S0 / T0 to S8 / T8) 7 (S9 / T9 to S15 / T15) 8 (S16 to S23) 28 (S24 to S51) 12(PFn, PG0 to 3) 24 (PCn, PDn, PEn) 2 (CF1,CF2) 1 (RES#) 6 (VSS1 to 2, VDD1 to 4)
(6) VFD automatic display controller - Programmable segment/digit output pattern Output can be switched between digit/segment waveform output (pins 9 to 24 can be used for output of digit waveforms). parallel-drive available for large current VFD. - 16-step dimmer function available (7) Weak signal detection (MIC signals etc) - Counts pulses with width greater than a preset value - 2 bit counter (8) Timers - Timer 0: 16 bit timer / counter with capture register Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit Counter with 8-bit capture register Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register Mode 3: 16 bit counter with 16 bit capture register
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LC876764A/48A - Timer 1: PWM / 16 bit timer toggle output Mode 0: 2 channel 8 bit timer (with toggle output) Mode 1: 2 channel 8 bit PWM Mode 2: 16 bit timer (with toggle output) Toggle output also possible using lower order 8 bits. Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM output. - Timer 4: 8 bit timer with 6 bit prescaler - Timer 5: 8 bit timer with 6 bit prescaler - Timer 6: 8 bit timer with 6 bit prescaler - Timer 7: 8 bit timer with 6 bit prescaler - Base Timer 1) The clock signal can be selected from any of the following. Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0 2) Interrupts can be selected to occur at one of five different times. (9) High speed clock counter 1) Capable of counting maximum: 20MHz clock (Using main clock 10MHz) 2) Real time output (10) Serial-interface - SIO 0: 8 bit synchronous serial Interface 1) LSB first / MSB first function available 2) Internal 8 bit baud-rate generator (maximum transmit clock period 4 / 3 Tcyc) 3) Continuous automatic data communication (1-256 bits) - SIO 1: 8 bit asynchronous / synchronous serial interface Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2-512 Tcyc) Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8-2048Tcyc) Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2-512 Tcyc) Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection) (11) AD converter -8 bits x 14 channels (12) Remote control receiver circuit (connected to P73 / INT3 / T0IN terminal) -Noise rejection function (noise rejection filter time constant can selected from 1 / 32 / 128 Tcyc) (13) Watchdog timer - The watching timer period is set using an external RC. - Watchdog timer can produce interrupt, system reset
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LC876764A/48A (14) Interrupts: 21-source, 10-vectored interrupts 1) Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or lower priority interrupt request is refused. 2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence. No. Vector Selectable Level 1 00003H X or L 2 0000BH X or L 3 00013H H or L 4 0001BH H or L 5 00023H H or L 6 0002BH H or L 7 00033H H or L 8 0003BH H or L 9 00043H H or L 10 0004BH H or L Priority Level: X>H>L For equal priority levels, vector with lowest (15) Subroutine stack levels: 768 levels max. (16) Multiplication and division - 16 bit x 8 bit (executed in 5 cycles) - 24 bit x 16 bit (12 cycles) - 16 bit / 8 bit (8 cycles) - 24 bit / 16 bit (12 cycles) (17) Oscillation circuits - On-chip RC oscillation circuit for system clock use. - On-chip CF oscillation circuit for system clock use. (R f built in) - On-chip Crystal oscillation circuit low speed system clock use. (Rd, Rf external) - On-chip frequency -variable RC oscillation circuit for system clock use (18) System clock divider function - Able to reduce current consumption Available minimum instruction cycle time: 300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2s, 38.4s, 76.8s. (Using 10MHz main clock) (19) Standby function - HALT mode HALT mode is used to reduce power consumption. Program execution is stopped. Peripheral circuits still operate but VFD display and some serial transfer operations stop. 1) Oscillation circuits are not stopped automatically. 2) Release occurs on system reset or by interrupt. Interrupt signal INT0 INT1 INT2/ T0L/ INT4 INT3/ Base timer/ INT5 T0H T1L/ T1H SI00 SI01 ADC/ MIC/ T6/ T7 VFD automatic display controller/ Port0/ T4/ T5 address takes precedence.
Stack is located in RAM.
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LC876764A/48A -HOLD mode HOLD mode is used to reduce power consumption. Both program execution and peripheral circuits are stopped. 1)CF, RCand crystal oscillation circuits stop automatically. 2) Release occurs on any of the following conditions. (1) input to the reset pin goes low (2) a specified level is input at least one of INT0, INT1, INT2, INT4, INT5 (3) an interrupt condition arises at port 0 -X'tal HOLD made X'tal HOLD mode is used to reduce power consumption. Program execution is stopped. All peripheral circuits except the base timer are stopped. 1) CF and RC oscillation circuits stop automatically. 2) Crystal oscillator is maintained in its state at HOLD mode inception. 3) Release occurs on any an any of the following conditions (1) input to the reset pin goes low (2) a specified level is input to at least one of INT0, INT1, INT2, INT4, INT5 (3) an interrupt condition arises at port 0 (4) an interrupt condition arises at the base-timer (20) Factory shipment -delivery form QIP100E (21) Development tools - Evaluation chip: LC876093 - Emulator: EVA62S + ECB876600 (Evaluation chip board) + SUB876700 + POD100QFP : ICE-B877300 + SUB876700 + POD100QFP - Flash ROM version: LC87F67C8A
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Pin Assignment
S48/PG0 S49/PG1 S50/PG2 S51/PG3 P00 P01 P02 P03 VSS2 VDD2 P04 P05 P06 P07 P10/SO0 P11/SI0/SB 0 P12/SCK0 P13/SO1 P14/SI1/SB 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
LC876764A/48A
P16/T1PWML P17/T1PWMH/BUZ P30/INT4/T1IN P31/INT4/T1IN P32/INT4/T1IN P33/INT4/T1IN P34/INT5/T1IN P35/INT5/T1IN P36/INT5/T1IN P37/INT5/T1IN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7/MICIN P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/NKIN/AN12 P73/INT3/T0IN/AN13 S0/T0 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
S47/PF7 S46/PF6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 VDD4 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 S23/PC7 S22/PC6 S21/PC5 S20/PC4 FIX0
S19/PC3 S18/PC2 S17/PC1 S16/PC0 VDD3 S15/T15 S14/T14 S13/T13 S12/T12 S11/T11 S10/T10 S9/T9 S8/T8 S7/T7 S6/T6 S5/T5 S4/T4 S3/T3 S2/T2 S1/T1
SANYO: QIP100E
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LC876764A/48A
System Block Diagram
Interrupt Control
IR
PLA
Stand-by Control
Flash ROM
CF RC MRC X'tal Clock Generator
PC
Bus Interface
ACC
SIO0
Port 0
B Register
SIO1
Port 1
C Register
Timer 0
(High speed clock counter)
Port 3 ALU
Timer 1
Port 7
Base Timer
Port 8
PSW
VFD Controller
ADC
RAR
INT 0 - 5 Noise Rejection
Weak Signal
RAM
Timer 4
Timer 6
Stack Pointer
Timer 5
Timer 7
Watch Dog Timer
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LC876764A/48A
Pin Assignment
Pin name VSS1 VSS2 VDD1 VDD2 VDD3 VDD4 FIX0 PORT0 P00 to P07 I/O * Power supply (-) * Power supply (+) Function Option No No
I/O
* Test pin Set as VSS with the user's option. (see Note 1) * 8bit input/output port * data direction programmable in nibble units * Use of pull-up resistor can be specified in nibble units * Input for HOLD release * Input for port 0 interrupt * 15V withstand at N-channel open drain output * * * * 8bit input/output port data direction programmable for each bit Use of pull-up resistor can be specified for each bit Other pin functions P10 SIO0 data output P11 SIO0 data input/bus input/output P12 SIO0 clock input/output P13 SIO1 data output P14 SIO1 data input/bus input/output P15 SIO1 clock input/output P16: Timer 1 PWML output P17: Timer 1 PWMH output/Buzzer output
No Yes
PORT1 P10 to P17
I/O
Yes
PORT3 P30 to P37
I/O
* 8bit Input/output port * Data direction can be specified for each bit * Use of pull-up resistor can be specified for each bit * 15V withstand at N-channel open drain output * Other functions: P30 to P33: INT4 input/ HOLD release input/ Timer 1 event input/ Timer 0L capture input/ Timer 0H capture input P34 to P37: INT4 input/ HOLD release input/ Timer 1 event input/ Timer 0L capture input/ Timer 0H capture input The following types of interrupt detection are possible: Rising INT4 INT5 Yes Yes Falling Yes Yes Rising/ Falling Yes Yes H level No No L level No No
Yes
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LC876764A/48A
Pin name PORT7 P70 to P73 I/O I/O Function * 4bit Input/output port * Data direction can be specified for each bit * Use of pull-up resistor can be specified for each bit * Other functions P70: INT0 input/HOLD release input/Timer0L capture Input/output for watchdog timer P71: INT1 input/HOLD release input/Timer0H capture input P72: INT2 input/HOLD release input/timer 0 event input/Timer0L capture input/High speed clock counter input P73: INT3 input(noise rejection filter attached input)/timer 0 event input/Timer 0H capture input AD input port: AN8(P70), AN9(P71), AN12(P72), AN13(P73) The following types of interrupt detection are possible: Rising INT0 INT1 INT2 INT3 PORT8 P80 to P87 I/O Yes Yes Yes Yes Falling Yes Yes Yes Yes Rising/ Falling No No Yes Yes H level Yes Yes No No L level Yes Yes No No No Option No
S0/T0 to S8/T8 S9/T9 to S15/T15 S16 to S23
O O I/O
* 8bit Input/output port * Input/output can be specified in a bit unit * Other functions: AD input port: AN0 to AN7 Weak signal detector input port: MICIN(P87) * Large current output for VFD display controller digit (can be used for segment) * Large current output for VFD display controller segment/digit * Output for VFD display controller segment/digit * Other functions: High voltage input port: PC0 to PC7 * Output for VFD display controller segment * Other functions: High voltage input port: PD0 to PD7 * Output for VFD display controller segment * Other functions High voltage input port: PE0 to PE7 * Output for VFD display controller segment * Other functions: High voltage input/output port: PF0 to PF7 * Output for VFD display controller segment * Other functions: High voltage input/output port: PG0 to PG3 Reset terminal * Input for 32.768kHz crystal oscillation * Other functions: General purpose input port When not in use, connect to VDD1. AD input port: AN10
No No No
S24 to S31
I/O
No
S32 to S39
I/O
No
S40 to S47
I/O
No
S48 to S51
I/O
No
RES XT1
I I
No No
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LC876764A/48A
Pin name XT2 I/O I/O Function * Output for 32.768kHz crystal oscillation * Other functions: General purpose input port When not in use, set to oscillation mode and leave open circuit. AD input port: AN11 Input terminal for ceramic oscillator Output terminal for ceramic oscillator Option No
CF1 CF2
I O
No No
Note 1: The LC876700 series can be mounted onto the circuit board intended for the LC 876500 and LC876600 series. In this case, the minus voltage of the VFD power supply is supplied to the FIX0 pin. Using a negative voltage does not alter the FIX0 pin's operation.
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LC876764A/48A
Port Output Configuration
Output configuration and pull-up/pull-down resistor options are shown in the following table. Input /output is possible even when port is set to output mode.
Terminal P00 to P07 Option applies Options to: 1 bit units 1 2 P10 to P17 each bit 1 2 P30 to P37 each bit 1 2 P70 P71 to P73 P80 to P87 S0/T0 to S15/T15 S16 to S51 XT1 XT2 None None None High voltage Pch-open drain Input only Output for 32.768kHz crystal oscillation None None None None None None CMOS 15 voltage Nch-open drain CMOS Nch-open drain CMOS 15V Nch-open drain Nch-open drain CMOS Nch-open drain Output Format Pull-up resistor Programmable (Note 1) None Programmable Programmable Programmable None Programmable Programmable None Pull-down resistor -
Note 1 Programmable pull-up resisters of Port 0 can be attached in nibble units (P00-03, P04-07). * Note 1: Connect as follows to reduce noise on VDD and increase the back-up time. VSS1, and VSS2 must be connected together and grounded. *Note 2 : The power supply for the internal memory is VDD1 but it uses the VDD2 as the power supply for ports. When the VDD2 is not backed up, the port level does not become "H" even if the port latch is in the "H" level. Therefore, when the VDD2 is not backed up and the port latch is "H" level, the port level is unstable in the HOLD mode, and the back up time becomes shorter because the through current runs from VDD to GND in the input buffer. If VDD2 is not backed up, output "L" by the program or pull the port to "L" by the external circuit in the HOLD mode so that the port level becomes "L" level and unnecessary current consumption is prevented.
LSI VDD1 Back-up capacitors
Power Supply
VDD2 VDD3 VFD VDD4 VSS1 Powers VSS2
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LC876764A/48A
1. Absolute maximum ratings / Ta=25C and VSS1=VSS2=0V
Limits Parameter Supply voltage Input voltage Output voltage Input/Output voltage Symbol Pins Conditions VDD1=VDD2= VDD3=VDD4
VDD[V
]
min. -0.3 -0.3 VDD-45 VDD-45 -0.3
typ.
max. +7.0 VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3
unit V
VDDMAX VDD1,VDD2, VDD3,VDD4 VI(1) VI(2) VO(1) VIO(1) XT1,XT2,CF1, RES VP S0/T0 to S15/T15 *Port 0: CMOS output option *Port 1 *Port 3: CMOS output option *Port 7 *Port 8 *Port 0 open drain *Port 3 open drain S16 to S51 Port 0, 1, 3
VIO(2) VIO(3) High Peak IOPH(1) level output output current current IOPH(2) IOPH(3) IOPH(4)
-0.3 VDD-45 *CMOS output selected *Current at each pin Current at each pin Current at each pin Current at each pin Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins For each pin For each pin For each pin For each pin For each pin Ta = -30 to+70C -10
15 VDD+0.3 mA
Port71,72,73 S0/T0 to S15/T15 S16 to S51
-3 -30 -15 -30 -30 -5 -65 -60 -60 -60 20 5 50 50 20 mW
IOAH(1) Port 0 Total output IOAH(2) Port 1,3 current IOAH(3) Port 7 IOAH(4) S0/T0 to S15/T15 IOAH(5) S16 to S27 IOAH(6) S28 to S39 IOAH(7) S40 to S51 Low Port 7,8 level output Total IOAL(1) Port 00,01,02,03 current output IOAL(2) *Port 04,05,06,07 current *Port 1,3 IOAL(3) Ports 7,8 Maximum power dissipation Operating temperature range Storage temperature range Pdmax QIP100E Peak IOPL(1) output IOPL(2) current Port 0,1,3
Topr
-30
70
C
Tstg
-55
125
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LC876764A/48A
2. Recommended operating range / Ta=-30C to +70C, VSS1=VSS2=0V
Parameter Symbol Pins VDD1=VDD2=VDD3 =VDD4 VDD1 Conditions 0.294s Tcyc 200s RAM and the register data are kept in HOLD mode. Output disable Limits VDD[V] min. 4.5 typ. max. 6.0 unit V
Operating VDD(1) supply voltage range Hold voltage VHD
2.0
6.0
Input high voltage
VIH(1)
*Port 0,3: CMOS output option *Port 8 Port 0,3: N-ch open drain output *Port 1 *Port71,72,73 *P70 port input/ interrupt S16 to S51 P70 Weak signal input Port 70 Watchdog timer XT1, XT2, CF1, RES *Port 0,3: CMOS output option *Port 8 Port 0,3: N-ch open drain output *Port 1 *Port 71,72,73 *P70 port input /interrupt S16 to S51 Port 87 weak signal input Port 70 Watchdog timer XT1,XT2,CF1, RES
4.5-6.0 0.3VDD +0.7 4.5-6.0 0.3VDD +0.7 4.5-6.0 0.3VDD +0.7
VDD
VIH(2) VIH(3)
Output disable Output disable
13.5 VDD
VIH(4) VIH(5) VIH(6) VIH(7) Input low voltage VIL(1)
Output P-channel Tr. OFF Output disable Output disable
4.5-6.0 0.3VDD +1.0 4.5-6.0 0.75VDD 4.5-6.0 0.9VDD 4.5-6.0 0.75VDD
VDD VDD VDD VDD 0.15VDD +0.4 0.15VDD +0.4 0.1VDD +0.4
Output disable
4.5-6.0
VSS
VIL(2) VIL(3)
Output disable Output disable
4.5-6.0 4.5-6.0
VSS VSS
VIL(4) VIL(5) VIL(6) VIL(7) Operation cycle time External system clock frequency tCYC
Output P-channel Tr. OFF Output disabled Output disabled
4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0
-35 VSS VSS VSS 0.294 0.1
0.2VDD 0.25VDD 0.8VDD -1.0 0.25VDD 200 10 s
MHz
fEXCF(1) CF1
*CF2 open circuit 4.5-6.0 *system clock divider set to 1/1 *external clock DUTY = 5050% *CF2 open circuit 4.5-6.0 *system clock divider set to 1/2
0.2
20
Continued
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LC876764A/48A
Parameter Oscillation stabilizing time period (Note 1)
Symbol FmCF(1) FmCF(2)
Pins CF1, CF2 CF1, CF2
Conditions 10MHz ceramic resonator oscillation
Refer to figure 1
VDD[V] 4.5-6.0 4.5-6.0
Limits min. typ. 10 4
max.
unit MHz
4MHz ceramic resonator oscillation
Refer to figure 1
FmRC FmMRC FsX'tal XT1, XT2
RC oscillation Frequency variable RC oscillation 32.768kHz crystal resonator oscillation
Refer to figure 2
4.5-6.0 4.5-6.0 4.5-6.0
0.3
1.0 50 32.768
2.0
KHz
(Note 1) The oscillation constant is shown in table 1 and table 2.
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LC876764A/48A
3. Electrical characteristics / Ta=-30C to +70C, VSS1=VSS2=0V
Parameter Input high current Symbol IIH(1) Pins Ports 0,3: N-ch open drain output Conditions *Output disabled *VIN=13.5V (including OFF state leak current of the output Tr.) *Output disabled *Pull-up resister OFF. *VIN=VDD (including OFF state leak current of the output Tr.) When configured as an input port VIN=VDD VIN=VDD When configured as an input port VIN=VDD VIN=VDD VIN=VBIS+0.5V (VBIS : Bias voltage) *Output disabled *VIN=VSS (including OFF state leak current of the output Tr.) VIN=VSS When configured as an input port VIN=VSS VIN=VSS VIN=VBIS-0.5V (VBIS : Bias voltage) IOH=-1.0mA IOH=-0.1mA IOH=-0.4mA IOH=-20.0mA IOH=-1.0mA IOH at any single pin is not over 1mA. S2+ to S51 IOH=-5.0mA IOH=-1.0mA IOH at any single pin is not over 1mA. Port 0,1,3 Port 7,8 Port 0,1,3,7 IOL=10mA IOL=1.6mA IOL=1mA VOH=0.9VDD Limits VDD[V] 4.5-6.0 min. typ. max. 5 unit A
IIH(2)
Port 0,1,3,7,8
4.5-6.0
1
IIH(3)
S16 to S51 (Port C,D,E,F,G) RES XT1,XT2
4.5-6.0
60
IIH(4) IIH(5)
4.5-6.0 4.5-6.0
1 1
IIH(6) IIH(7) Input low current IIL(1)
CF1 P87/AN7/MICIN weak signal input Port 0,1,3,7,8
4.5-6.0 4.5-6.0 4.5-6.0 4.2 -1 8.5
15 15
IIL(2) IIL(3)
RES XT1,XT2
4.5-6.0 4.5-6.0
-1 -1
IIL(4) IIL(5) Output high VOH(1) voltage VOH(2) VOH(3) VOH(4) VOH(5)
CF1 P87/AN7/MICIN weak signal input Port 0,1,3: CMOS output option Port 7 S0/T0-S15/T15
4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0
-15 -15 VDD-1 VDD-1 VDD-1 -8.5 -4.2 V
4.5-6.0 VDD-0.5 4.5-6.0 VDD-1.8
VOH(6) VOH(7)
4.5-6.0 VDD-1.8 4.5-6.0 VDD-1
Output low voltage Pull-up resistor
VOL(1) VOL(2) VOL(3) Rpu
4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 15 40
1.5 0.4 0.4 70 k
Continued
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LC876764A/48A
Parameter Output offleak current
Symbol IOFF(1) IOFF(2)
Pins S0/T0 to S15/T15, S16 to S51
Conditions *Output P-ch Tr. OFF *VOUT=VSS *Output P-ch Tr. OFF *VOUT=VDD-40V *Output P-ch Tr. OFF
VDD[V] 4.5-6.0 4.5-6.0 4.5-6.0
Limits min. -1 -30
typ.
Max. unit A
Resistance of Rinpd the low level hold Tr. Hysteresis VHIS(1) voltage VHIS(2) Pin capacitance CP
S16 to S51
200
k
*Port 1,7 * RES Port 87 weak signal input All pins
4.5-6.0 4.5-6.0 *All other terminals connected to VSS. *f=1MHz *T a =25C 4.5-6.0
0.1VDD 0.1VDD 10
V
pF
Input sensitivity
Vsen
Port 87 weak signal input
4.5-6.0
0.12VDD
Vpp
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LC876764A/48A
4. Serial input/output characteristics / Ta=-30C to +70C, VSS1=VSS2=0V
Parameter Cycle Time Low Level pulse width High Level pulse width Cycle Time Symbol tSCK(1) tSCKL(1) tSCKLA(1) tSCKH(1) tSCKHA(1) tSCK(2) tSCKL(2) tSCKH(2) tSCK(3) tSCKL(3) tSCKLA(2) tSCKH(3) tSCKHA(2) tSCK(4) tSCKL(4) tSCKH(4) tsDI thDI tdDO SI0(P11), SI1(P14), SB0(P11), SB1(P14) SO0(P10), SO1(P13), SB0(011), SB1(P14) *Measured with respect to SI0CLK leading edge. *Refer to figure 6 *Measured with respect to SI0CLK trailing edge. *When port is open drain: Time delay from SI0CLK trailing edge to the SO data change. *Refer to figure 6 4.5-6.0 0.03 0.03 4.5-6.0 1/3 tCYC +0.05 SCK1(P15) *CMOS output option *Refer to figure 6 4.5-6.0 2 1/2 1/2 s SCK0(P12) *CMOS output option *Refer to figure 6 4.5-6.0 SCK1(P15) Refer to figure 6 4.5-6.0 Pins Conditions VDD[V] 4.5-6.0 min. 4/3 2/3 2/3 2/3 3 2 1 1 4/3 1/2 3/4 1/2 2 tCYC tSCK tSCK Limits typ. max. unit tCYC
SCK0(P12) Refer to figure 6
Serial clock Serial input
Output clock
Input clock
Low Level pulse width High Level pulse width Cycle Time Low Level pulse width High Level pulse width Cycle Time Low Level pulse width High Level pulse width Data set-up time Data hold time Output time delay
Serial output
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LC876764A/48A
5. Pulse input conditions / Ta=-30C to +70C, VSS1=VSS2=0V
Parameter High/low level pulse width Symbol Pins Conditions VDD[V] tPIH(1) INT0(P70), tPIL(1) INT1(P71), INT2(P72) INT4(P30 to P33) INT5(P34 to P37) tPIH(2) INT3(P73) tPIL(2) (Noise rejection ratio set to 1/1.) tPIH(3) INT3(P73) tPIL(3) (Noise rejection ratio set to 1/32.) tPIH(4) INT3(P73) tPIL(4) (Noise rejection ratio set to 1/128.) tPIH(5) MICIN(P87) tPIL(5) tPIH(6) NKIN(P72) tPIL(6) tPIL(7) RES *Interrupt acceptable 4.5-6.0 *Events to timer 0 can be input. Limits min. 1 typ. max. unit tCYC
*Interrupt acceptable 4.5-6.0 *Events to timer 0 can be input. *Interrupt acceptable 4.5-6.0 *Events to timer 0 can be input. *Interrupt acceptable 4.5-6.0 *Events to timer 0 can be input. *Weak signal detection counter enabled *High speed clock counter countable *Reset possible 4.5-6.0
2
64
256
1
4.5-6.0 4.5-6.0
1/12 200 s
6. AD converter characteristics / Ta=-30C to + 70C, VSS1=VSS2=0V
Parameter Resolution Absolute precision Conversion time Symbol N ET TCAD Pins AN0(P80) to AN7(P87), AN8(P70), AN9(P71), AN10(XT1), AN11(XT2), AN12(P72), AN13(P73) Conditions Limits VDD[V] 4.5-6.0 (Note2) AD conversion time = 32 x tCYC (ADCR2=0) (Note 3) AD conversion time = 64 x tCYC (ADCR2=1) (Note 3) 4.5-6.0 VAIN=VDD VAIN=VSS 4.5-6.0 4.5-6.0 -1 4.5-6.0 4.5-6.0 15.62 (tCYC= 0.488s) 18.82 (tCYC= 0.294s) VSS min. typ. 8 1.5 97.92 (tCYC= 3.06s) 97.92 (tCYC= 1.53s) VDD 1 V A max. unit bit LSB s
Analog input voltage range
VAIN
Analog port input IAINH current IAINL
(Note 2) Absolute precision not including quantizing error (1/2 LSB). (Note 3) Conversion time means time from executing AD conversion instruction to loading complete digital value to register.
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7. Current dissipation characteristics / Ta=-30C to +70C, VSS1=VSS2=0V
Parameter Current dissipation during basic operation (Note 4) Symbol IDDOP(1) Pins Conditions Limits VDD[V ] 4.5-6.0 min. typ. 9 max 30 unit mA
IDDOP(2)
IDDOP(3)
IDDOP(4)
IDDOP(5)
IDDOP(6)
VDD1 *FmCF=10MHz for Ceramic resonator = VDD2 oscillation *FsX'tal=32.768kHz for = VDD3 crystal oscillation *System clock: CF = VDD4 oscillation *Internal RC oscillation stopped. *Frequency variable RC oscillation stopped. *Divider set to 1/1 *CF1=20MHz for external clock *FsX'tal=32.768kHz for crystal oscillation *System clock: CF oscillation *Internal RC oscillation stopped. *Frequency variable RC oscillation stopped. *Divider set to 1/2 *FmCF=4MHz Ceramic resonator oscillation *FsX'tal=32.768kHz for crystal oscillation *System clock: CF oscillation *Internal RC oscillation stopped. *Frequency variable RC oscillation stopped. *Divider set to 1/1 *FmCF=0Hz (No oscillation) *FsX'tal=32.768kHz for crystal oscillation *Frequency variable RC oscillation stopped. *System clock: RC oscillation *Divider set to 1/2 *FmCF=0Hz (No oscillation) *FsX'tal=32.768kHz for crystal oscillation *Internal RC oscillation stopped. *System clock: 1MHz with frequency variable RC oscillation *Divider set to 1/2 *FmCF=0Hz (No oscillation) *FsX'tal=32.768kHz for crystal oscillation *System clock: 32.768KHz *Frequency variable RC oscillation stopped. *Divider set to 1/2
4.5-6.0
10
31
4.5-6.0
4
17
4.5-6.0
1
10
4.5-6.0
2
12
40
140
A
Continued
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LC876764A/48A
Parameter Current dissipation HALT mode (Note 4)
Symbol
Pins
Conditions HALT mode *FmCF=10MHz for Ceramic resonator oscillation *FsX'tal=32.768kHz for crystal oscillation *System clock : CF oscillation *Internal RC oscillation stopped. *Frequency variable RC oscillation stopped. *Divider: 1/1 HALT mode *CF1=20MHz for external clock *FsX'tal=32.768kHz for crystal oscillation *System clock : CF oscillation *Internal RC oscillation stopped. *Frequency variable RC oscillation stopped. *Divider 1/2 HALT mode *FmCF=4MHz for Ceramic resonator oscillation *FsX'tal=32.768kHz for crystal oscillation *System clock : 4MHz *Internal RC oscillation stopped. *Frequency variable RC oscillation stopped. *Divider: 1/1 HALT mode *FmCF=0Hz (When oscillation stops.) *FsX'tal=32.768kHz for crystal oscillation *System clock : RC oscillation *Divider: 1/2 HALT mode *FmCF=0Hz (When oscillation stops.) *FsX'tal=32.768kHz for crystal oscillation *Internal RC oscillation stopped. *System clock: 1MHz with frequency variable RC oscillation *Divider: 1/2
IDDHALT(1) VDD1= VDD2= VDD3= VDD4
VDD[V] min. 4.5 to 6.0
Limits typ. max. 4 12
unit mA
IDDHALT(2)
4.5 to 6.0
4.8
13
IDDHALT(3)
4.5 to 6.0
1.8
6
IDDHALT(4)
4.5 to 6.0
500
1600
A
IDDHALT(5)
4.5 to 6.0
1500
3600
Continued
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Parameter Current dissipation HALT mode (Note 4)
Symbol
Pins
Conditions HALT mode *FmCF=0Hz (When oscillation stops.) *FsX'tal=32.768kHz for crystal oscillation *System clock : 32.768kHz *Internal RC oscillation stopped. *Frequency variable RC oscillation stopped. *Divider: 1/2
IDDHALT(6) VDD1= VDD2= VDD3= VDD4
VDD[V] min. 4.5 to 6.0
Limits typ. max. 25 100
unit A
Current IDDHOLD(1) dissipation HOLD mode Current IDDHOLD(2) dissipation Date/time clock HOLD mode
VDD1
VDD1
HOLD mode 4.5 to 6.0 *CF1=VDD or open circuit (when using external clock) Date/time clock HOLD 4.5 to 6.0 mode *CF1=VDD or open circuit (when using external clock) *FmX'tal=32.768kHz for crystal oscillation
0.05
25
20
90
(Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored.
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LC876764A/48A Main system clock oscillation circuit characteristics The characteristics in the table bellow is based on the following conditions: 1. Use the standard evaluation board SANYO has provided. 2. Use the peripheral parts with indicated value externally. 3. The peripheral parts value is a recommended value of oscillator manufacturer Table 1. Main system clock oscillation circuit characteristics using ceramic resonator
Frequenc y Manufacture r Oscillator Circuit parameters C1 C2 Rd1 Operating Oscillation supply stabilizing time voltage typ max range Notes
10MHz
4MHz
The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage. (Refer to Figure4) Subsystem clock oscillation circuit characteristics The characteristics in the table bellow is based on the following conditions: 1. Use the standard evaluation board SANYO has provided. 2. Use the peripheral parts with indicated value externally. 3. The peripheral parts value is a recommended value of oscillator manufacturer Table 2. Subsystem clock oscillation circuit characteristics using crystal oscillator
Frequency Manufacturer Oscillator C3 32.768kHz Circuit parameters C4 Rf Rd2 Operating supply voltage range Oscillation stabilizing time typ max Notes
The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after releasing the HOLD mode. (Refer to Figure4) (Notes) * Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length.
CF1
CF2 Rd1
XT1 Rf
XT2
Rd2 C4
C1
CF
C2
C3 X'tal
Figure 1
Ceramic oscillation circuit
Figure 2
Crystal oscillation circuit
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LC876764A/48A
0.5VDD
Figure 3
AC timing measurement point
VDD Power l Reset time RES VDD limit 0V
Internal RC Resonator tmsCF CF1,CF2 tmsXtal XT1,XT2
Operation mode
Unfixed
Reset
Instruction execution mode
Reset time and oscillation stable time
HOLD release i l
Without HOLD Release
HOLD release signal VALID
Internal RC Resonator tmsCF CF1,CF2 tmsXtal XT1,XT2
Operation mode
HOLD
HALT
HOLD release signal and oscillation stable time
Figure 4
Oscillation stablization time
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LC876764A/48A
VDD
RRES
RES CRES
(Note) Set CRES, RRES values such that reset time exceeds 200s.
Figure 5
Reset circuit
SIOCLK
DATAIN
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7 Data RAM transmission period (only SIO0)
DO8
tSCK tSCKL SIOCLK tsDI DATAIN tdDO DATAOUT thDI tSCKH
Data RAM transmission period (only SIO0) tSCKLA SIOCLK tsDI DATAIN tdDO DATAOUT thDI tSCKHA
Figure 6
Serial input / output test condition
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LC876764A/48A
tPIL
tPIH
Figure 7
Pulse input timing condition
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LC876764A/48A
This catalog provides information as of August 2001. Specifications and information herein are subject to change without notice
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